A ball grid array (BGA) semiconductor package is normally incorporated with a semiconductor chip on a substrate and electrically connects the chip to the substrate via a plurality of bonding wires.
With increasing integration of a chip having higher density of bond pads, more bonding wires need to be formed accordingly and a pitch between adjacent bonding wires is reduced to accommodate more bonding wires on a limited-sized chip. However, the reduced pitch makes adjacent bonding wires more closely arranged with respect to each other; in a subsequent molding process, these closely arranged bonding wires would be easily subject to wire sweep or wire short, thereby adversely affecting quality of a fabricated semiconductor package.
In response to the above problem, U.S. Pat. No. 5,581,122 discloses a semiconductor package in which a ground ring 17 and a power ring 18 are formed on a substrate 10 between bond fingers 102 for being bonded with bonding wires 110 and an area where a chip 11 is mounted, as shown in FIG. 1. Ground wires 112 and power wires 111 are formed to electrically connect ground pads and power pads (not shown) on an active surface of the chip 11 respectively to the ground ring 17 and power ring 18 on the substrate 10, which are arranged spatially in different layers with respect to the bonding wires 110 to thereby increase a pitch between adjacent wires and prevent circuit short due to wire sweep or shift.
However, as the chip is developed with lower profile and higher density of bonding wires, a pitch between adjacent bond pads formed on an active surface of the chip is decreased from 60 μm to 40 μm and even to 30 μm to accommodate more I/O (input/output) connections thereon, in order to reduce fabrication costs and enhance chip performances. As a result, the above layered arrangement of bonding wires is not suitably applied to such a delicate chip with a fine pad pitch.
Moreover, in accordance with the reduced pad pitch of the chip, a pitch between bond fingers formed on the substrate is decreased from 150 μm to 125 μm and even to 100 μ m for a new generation of substrates; such a small bond-finger pitch arrangement makes bonding wires bonded thereto easily come into contact with each other and cause circuit short, and the above package structure still fails to solve this problem.
In another aspect, if the bond-pad pitch is further reduced to 30 μm, a current wire bonder may not be feasible to perform such a delicate wire bonding process, and also a conventional etching technique may hardly achieve a pitch below 100 μm between adjacent bond fingers on the substrate.
The above wire-bonding problem may be solved through the use of flip-chip technology. However, the flip-chip technology requires a complex solder bumping process used for electrically connecting the chip to the substrate, and the substrate serving as a chip carrier needs to be manufactured by build-up technology instead of conventional fabrication processes, which would increase production costs of the substrate up to around five times more than that of a conventional substrate; such an expensive substrate is hardly acceptable in the market.